Feature sizes of semiconductor memory have been reduced to produce smaller memory components and/or provide more memory capacity in the same area. Voltage levels provided to semiconductor memory have also been reduced to limit power consumption. As the size and/or voltage of memory cells are reduced, the level of charge stored in each memory cell may also be reduced. This decreases margin of error of detecting the data state of the memory cells based on the stored charge. The reduced margin of error may make a memory device more prone to soft errors, for example, alpha particle interaction. The memory device may also be prone to other errors due to weak cells such as variable refresh times (VRT). An error may occur when one or more memory cells lose the charge stored in the cell before the cell is refreshed during a regular memory refresh cycle. The cell may lose its charge at an abnormal rate due to high leakage currents, poor initial charging, and/or additional defects in the cell. These errors may cause random single bit errors in the memory device.
Error correction code (ECC) may be used with the memory to compensate for and/or correct data errors in the memory cells. Examples of ECC include Hamming codes and parity bits. While ECC may improve data integrity of the memory, it may also increase the time required for one or more memory operations. This may reduce memory performance.